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1 publication order number : lc78616pe/d www.onsemi.com ? semiconductor component s industries, llc, 2016 august 2016 - rev. 0 ordering information see detailed ordering and shipping info rmation on page 27 of this data sheet. lc78616pe digital servo processor lsi for compact disc player with rf amplifier overview the lc78616pe integrates rf signal processor for cd-da/r/rw, servo control, efm signal processing, anti-shock processing and playback controller (sequencer : 8bits cpu). it is possible to make cd player system using with micro controller, driver and sdram ic?s with less components. features ? rf signal processing for cd-da/r/rw, servo control and efm signal processing ? outputs cdda, cdrom data ? maximum approximately 40 seconds shock protection by shock proof function with external 64m bits sdram ? cd-text decoded data are stored in external sdram. ? cd playback system is realized with simple macro commands by the external controller because of the internal sequencer (8 bits - cpu). ? operating voltage : 3.3 v typical ? operating temperature : ? 40 ? c to +85 ? c ? package : qip100e(14 ? 20) pqfp100 14x20 / qip100e
lc78616pe www.onsemi.com 2 detail of functions [cd-dsp functions] < playback functions> ? playback mode : clv playback / jitter free playback (vcec) ? playback speed : normal speed, double speed, quad ruple speed (clv playback / jitter free playback) ? rf system : agc, cd-r and cd-r/w playback support, peak hold, bottom hold ? error system : te signal generation, fe signal generation ? detection : track count signal, jitter, defect (black, mirror) ? laser power controller (apc) ? dc offset voltage cancellation ? all servo systems as tracking, focus, sled and spindle are implemented with digital processing. ? automatic adjustment functions : focus gain, focus bias, focus offset, tracking gain, tracking offset and tracking balance ? shock detection / interruption detection ? efm signal synchronization detection, protection and interpolation ? error detection, correction (c1 = double, c2 = quadruple/double) ? jitter margin 19 frames ? buffers cd-text decoded data to the buffer memory. ? starts buffering of cd-text decoded data from desired id3/id4. ? shock proof processing using with external 16m-bit or 64m-bit memory approximately 10sec. with 16mbit or 40sec. with 64mbit [cd data processing functions] ? interpolation ? mute function ( ? 12 db, ? ) ? digital attenuator ? de-emphasis filter ? clv playback : fixed normal speed or double speed ? jitter free playback (vcec) : fr ee speed within quadruple speed *cdrom data is not buffering to sdram and output directly ? digital 3 lines output(lrck,bck,data) ? supports various external audio data output format iis (48 fs), msb first, right-justified, left-j ustified (32 fs / 48 fs), 16-bit data length ? slave mode output data synchronized to external clock input (lrck and bck) ? digital output (s/pdif, only clv playback mode) [internal microcontroller functions] ? cd playback control servo control, cd-text processing, digital data output control, etc. ? the sio interface using ce, cl, di, do and busy b pins is available as communication format. ? external main controller can control th is ic directly such as ?stop oscillation? or ?restart oscillation? or so on at the internal register open mode (reg_ready high condition). ? even while the oscillation is stopped, some of general port can be controlled by host controller. ? gpio port 8 ports maximum (shared with other functions.) ? mask-rom type ? rom correct function is built in for the partial chan ge of the program and host controller can use this. ? watch dog timer notifies to outside from a pin or resets internally. ? power management (two kinds of sleep mode) (1) only the clock for cpu core is operating and clocks for other blocks are stopping. (2) all clocks are stopping. [others] ? 1.5 v regulator for internal blocks
lc78616pe www.onsemi.com 3 specifications absolute maximum ratings at ta = 25c, dv ss = av ss = xv ss = vv ss 1 = 0 v parameter symbol conditions ratings unit maximum supply voltage v dd max dvdd, avdd, xvdd, vvdd1 ? 0.3 to +3.95 v input voltage 1 v in 1 ? 0.3 to dv dd +0.3 output voltage v out ? 0.3 to dv dd +0.3 allowable power dissipation pd max ta 85c mounted reference pcb(*) 300 mw operating temperature topr ? 40 to +85 c storage temperature tstg ? 40 to +125 (*) reference pcb : 114.3 mm 76. 1 mm 1.6 mm, glass epoxy resin stresses exceeding maximum rati ngs may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditio ns is not implied. extended exposu re to stresses a bove the recommended operating conditions may affe ct device reliability. allowable operating ranges at ta = ? 40 to 85c, dv ss = av ss = xv ss = vv ss 1 = 0 v parameter symbol pi n names type conditions min typ max unit supply voltage v dd dvdd, avdd, xvdd, vvdd1 3.00 3.60 v high-level input voltage v ih xin,resb, mode, mode3, ce, cl, di, cont00, cont01, cont02, cont03, cont04, cont05, cont08, cont09, cont10, do, sddat00 to 15, sdadrs11, sdadrs12 schmitt 2.00 v dd low-level input voltage v il xin, resb, test, mode3, ce, cl, di, cont00, cont01, cont02, cont03, cont04, cont05, cont08, cont09, cont10, do, sddat00 to 15, sdadrs11, sdadrs12 schmitt 0.00 0.80 crystal oscillator frequency fx xin oscillator circuit 16.9344 mhz xout external clock input exck xin schmitt 16.9344 18.0 mhz stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected. functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recomme nded operating ranges limits may affect device r eliab ility.
lc78616pe www.onsemi.com 4 electrical characteristics at ta = ? 40 to 85c, v dd = 3.0 to 3.6 v, dv ss = av ss = xv ss = vv ss 1 = 0 v parameter symbol pi n names type conditions min typ max unit current drain i dd 1 dvdd, avdd, xvdd, vvdd1 40 60 ma high-level input current i ih resb, mode, mode3, ce, cl, di, cont00, cont01, cont02, cont03, cont04, cont05, cont08, cont09, cont10, do, sddat00 to 15, sdadrs11, sdadrs12 schmitt v in = v dd built-in pull-down resistor off 10.00 a low-level input current i il resb, test, mode3, ce, cl, di, cont00, cont01, cont02, cont03, cont04, cont05, cont08, cont09, cont10, sddat00 to 15, sdadrs11, sdadrs12 schmitt v in = 0.0v built-in pull-down resistor off ? 10.00 high-level output voltage v oh (1) do, busyb, cont00, cont01, cont02, cont03, cont05, cont08, cont09, cont10, sddat00 to sddat15, sdadrs00 to sdadrs12, sdba, sdcke, sdcsb, sdrasb, sdcasb, sdweb, sddqm cmos ioh = ? 2 ma v dd ? 0.6 v v oh (2) cl, di, cont04, sdclk cmos ioh = ? 4 ma low-level output voltage v ol (1) do, busyb, cont00, cont01, cont02, cont03, cont05, cont08, cont09, cont10, sddat00 to sddat15, sdadrs00 to sdadrs12, sdba, sdcke, sdcsb, sdrasb, sdcasb, sdweb, sddqm cmos iol = 2 ma 0.40 v ol (2) cl, di, cont04, sdclk cmos iol = 4 ma output off-leakage current i off (1) pdout0, pdout1 hi-z out ? 10.00 10.00 a i off (2) do hi-z out ? 10.00 10.00 built-in pull-down resistor rpd ce, cont00, cont01, cont02, cont03, cont04, cont05, cont08, cont09, cont10, sddat00 to sddat15, sdadrs11,sdadrs12 50 100 200 k ? charge pump output current ipdoh pdout1, pdout0 pckist = 100 k ? current value setting : 1x 35 50 65 a ipdol pdout1, pdout0 ? 65 ? 50 ? 35 (notes) ? connect and use the pull-up or the pull-down resister with the outside when you use serial communications because the terminal do is 3- state output (initial state). ? the do, busyb, cont00, cont01, cont02, cont03, cont 04, cont05, cont08, cont09 and cont10 pins can be used as the n channel open drain pins. when used as the n channe l open drain pin, external pull-up resistor must be connected t o those pins. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions.
lc78616pe www.onsemi.com 5 package dimensions unit : mm pqfp100 14x20 / qip100e case 122bv issue a xxxxx = specific device code y = year m = month ddd = additional traceability data generic marking diagram* *this information is generic. please refer to device data sheet for actual part marking. may or may not be present. xxxxxxxxx ymddd (unit: mm) 22.30 16.30 0.43 0.65 1.30 soldering footprint* note: the measurements are not to guarantee but for reference only. *for additional information on our pb -free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 20.0 0.1 12 0.65 (0.58) 0.13 14.0 0.1 17.2 0.2 23.2 0.2 100 0.3 0.05 0.10 3.0 max (2.7) 0.1 0.1 0 to 10 0.15 0.8 0.2
lc78616pe www.onsemi.com 6 pin assignment 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 avdd fdo tdo sldo spdo vvss1 pdout1 pdout0 pckist vvdd1 mode ce cl di do resb test busyb cont04 cont05 cont03 cont02 cont01 cont00 sddat15 dvdd dvss dvdd15 sddat14 sddat13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 avss lds ldd tein te nc fin ein jittc vref rfmon slciset din bin cin ain phlpf lpf rfout efmin slco dvss cont10 cont09 cont08 dvdd xvdd xin xout xvss sdadrs12/cont07 sdadrs11/cont06 sddat00 sddat01 sddat02 sddat03 sddat04 dvdd dvss dvdd15 sddat05 sddat06 sddat07 sddqm sdweb sdcasb sdrasb sdcsb sdba mode3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 dvdd dvss sddat12 sddat11 sddat10 sddat09 sddat08 sdclk sdcke sdadrs09 sdadrs08 sdadrs07 sdadrs06 sdadrs05 sdadrs04 sdadrs03 sdadrs02 sdadrs01 sdadrs00 sdadrs10 lc78616 6dxx
lc78616pe www.onsemi.com 7 pin description pin no. pin name i/o state when ?reset? function 1 avdd ? ? analog system power supply 2 fdo ao avdd/2 focus control signal output 3 tdo ao avdd/2 tracki ng control signal output 4 sldo ao avdd/2 sled control signal output 5 spdo ao avdd/2 spindl e control signal output 6 vvss1 ? ? efmpll ground. this pin must be connected to the 0v level. 7 pdout1 ao undefined efmpll charge pump output 1 8 pdout0 ao undefined efmpll charge pump output 0 9 pckist ai input efmpll charge pump current se tting resistor connection pin 10 vvdd1 ? ? efmpll power supply 11 mode i input lsi mode set pin. this pin mu st be connected to the dvdd level. 12 ce i input host i/f enable signal input for serial communication this pin must be connected to the 0v level in iic communication mode. 13 cl i/o input host i/f data transfer clock input for serial communication data transfer clock input for iic communication (n-ch. open drain) 14 di i/o input host i/f data input for se rial communication data input/output for iic communication (n-ch. open drain) 15 do i/o input host i/f data output for serial communication this pin must be pulled down to the 0v level or be pulled up to the dvdd level in iic communication mode. 16 resb i input ic reset input.(low active) this pin must be set low once after power is first applied. 17 test i input test input. this pin must be connected to the 0v level. 18 busyb o low host i/f busyb output(high : comm unication available) 19 cont04 i/o input general purpose i/o port with pull down resistor digital audio output fs384 clock output for audio dac clock input/output for cdtext interface (exclusive with cont01 and cont09) watch dog timer state monitor output 20 cont05 i/o input general purpose i/o port with pull down resistor serial data output for cdtext interface 21 cont03 i/o input general purpose i/o port with pull down resistor digital audio output fs384 clock output for audio dac sbck clock input for cd subcode data data request signal input for cdtext interface (exclusive with cont00 and cont08) watch dog timer state monitor output 22 cont02 i/o input general purpose i/o port with pull down resistor data output for di gital audio interface pw data output in cd subcode serial data output for cdtext interface 23 cont01 i/o input general purpose i/o port with pull down resistor bit clock output for cd data bit clock input for cd data (exclusive with cont09) frame synchronization signal (sfsy) output for cd subcode clock input/output for cdtext interface (exclusive with cont04 and cont09) 24 cont00 i/o input general purpose i/o port lr clock output for cd data lr clock input for cd data (exclusive with cont08) block synchronization signal (s bsy) output for cd subcode data request signal input for cdtext in terface (exclusive with cont03 and cont08) 25 sddat15 i/o input(low) sdram data 15
lc78616pe www.onsemi.com 8 pin no. pin name i/o state when ?reset? function 26 dvdd ? ? digital system power supply 27 dvss ? ? digital system ground. this pin must be connected to the 0v level. 28 dvdd15 ao high capacitor connection pin for internal regulator 29 sddat14 i/o input(low) sdram data 14 30 sddat13 i/o input(low) sdram data 13 31 dvdd ? ? digital system power supply 32 dvss ? ? digital system ground. this pin must be connected to the 0v level. 33 sddat12 i/o input(low) sdram data 12 34 sddat11 i/o input(low) sdram data 11 35 sddat10 i/o input(low) sdram data 10 36 sddat09 i/o input(low) sdram data 9 37 sddat08 i/o input(low) sdram data 8 38 sdclk o low sdram system clock output 39 sdcke o low sdram clock enable output 40 sdadrs09 o low sdram address output 9 41 sdadrs08 o low sdram address output 8 42 sdadrs07 o low sdram address output 7 43 sdadrs06 o low sdram address output 6 44 sdadrs05 o low sdram address output 5 45 sdadrs04 o low sdram address output 4 46 sdadrs03 o low sdram address output 3 47 sdadrs02 o low sdram address output 2 48 sdadrs01 o low sdram address output 1 49 sdadrs00 o low sdram address output 0 50 sdadrs10 o low sdram address output 10 51 mode3 i input lsi mode set pin 52 sdba o low sdram bank select address output connect sdram-bank pin when 16mbit sdram using connect sdram-bank1 pin when 64mbit sdram using 53 sdcsb o low sdram chip select output 54 sdrasb o low sdram row address strobe output 55 sdcasb o low sdram column address strobe output 56 sdweb o low sdram write enable output 57 sddqm o low sdram data mask control output common both for 16m/64mbit-sdram : connect this pin both to sdram-dqmh(udqm) and dqml(ldqm) pins 58 sddat07 i/o input(low) sdram data 7 59 sddat06 i/o input(low) sdram data 6 60 sddat05 i/o input(low) sdram data 5 61 dvdd15 ao high capacitor connection pin for internal regulator 62 dvss ? ? digital system ground. this pin must be connected to the 0v level. 63 dvdd ? ? digital system power supply 64 sddat04 i/o input(low) sdram data 4 65 sddat03 i/o input(low) sdram data 3 66 sddat02 i/o input(low) sdram data 2 67 sddat01 i/o input(low) sdram data 1 68 sddat00 i/o input(low) sdram data 0 69 sdadrs11 i/o input(low) connect to sdram adrs11 pin when using 64m bit sdram. sdram address output 11 cont06 is available when using 16m bit sdram. general purpose i/o port with pull down resistor 70 sdadrs12 i/o input(low) connect to sdram bank0 pin when using 64m bit sdram. sdram address output 12 cont07 is available when using 16m bit sdram. general purpose i/o port with pull down resistor 71 xvss ? ? oscillator ground. this pin must be connected to the 0v level. 72 xout o oscillation 16.9344mhz oscillator connection 73 xin i oscillation 16.9344mhz oscillator connection 74 xvdd ? ? oscillator power supply 75 dvdd ? ? digital system power supply
lc78616pe www.onsemi.com 9 pin no. pin name i/o state when ?reset? function 76 cont08 i/o input general purpose i/o port with lr clock output for cd data lr clock input for cd data (exclusive with cont00) data request signal input for cdtext in terface (exclusive with cont00 and cont03) 77 cont09 i/o input general purpose i/o port with pull down resistor bit clock output for cd data bit clock input for cd data (exclusive with cont01) clock input/output for cdtext interface (exclusive with cont01 and cont04) 78 cont10 i/o input general purpose i/o port with pull down resistor data output for di gital audio interface digital audio output serial data output for cdtext interface watch dog timer state monitor output 79 dvss ? ? digital system ground. this pin must be connected to the 0v level. 80 slco ao undefined s lice level control output 81 efmin ai input rf signal input 82 rfout ao undefined rf signal output 83 lpf ao undefined rf signal dc level de tection low-pass filter capacitor connection 84 phlpf ao undefined def ect detection low-pass filt er capacitor connection 85 ain ai input a signal input 86 cin ai input c signal input 87 bin ai input b signal input 88 din ai input d signal input 89 slciset ai input slco output cu rrent setting resistor connection 90 rfmon ao undefined ic inte rnal analog signal monitor 91 vref ao avdd/2 referenc e voltage output for rf 92 jittc ao undefined jitter de tection capacitor connection 93 ein ai input e signal input 94 fin ai input f signal input 95 nc ? ? nc pin (open) 96 te ao undefined te signal output 97 tein ai input te signal input used for tes signal generation 98 ldd ao undefined laser power control signal output 99 lds ai input laser power detection signal input 100 avss ? ? analog system ground. this pin must be connected to the 0v level. (1) for unused pins : ? the unused input pins must be connect ed to the gnd(0v) level if there is no individual note in the above table. ? the unused output pins must be left open(no connection) if there is no individual note in the above table. ? the unused input/output pins must be connected to the gnd(0v) or power supply pin for i/o bloc k with internal pull down/up resistor off or be left open with internal pull down/up resist or on when input pin mode or mu st be left open(no connection ) when output pin mode if there is no i ndividual note in the above table. when you connect an i/o pin which is an input pin without internal pull-down/up resi stor at reset mode to the gnd or power supply level, we recommend you to use pull-down resist or or pull-up resistor individually as fail-safe. (2) for power supply pins : ? same voltage level must be supplied to dvdd, avdd, xvdd and vvdd1 power supply pins. (3) for ?reset? condition : ? this ic is not reset only by making the resb pin ?low?. refer to ?4. power on and reset contro l? for detail of ?reset? condition.
lc78616pe www.onsemi.com 10 block diagram cd rf signal processor ad/da cd servo controller cd pll cd efm/ecc decoder cdda anti shock cd-text decoder data trans controller external sdram data output control ? cdrom data ? cdda data de-emphasis/ mute/att dout(s/pdif) 8bit-cpu core bufram i/f program rom work ram host-i/f (sio) x'tal (16.9344mhz) regulator 1.5v 3.3v audio data-i/f external-in port control watch dog timer interrupt
lc78616pe www.onsemi.com 11 power on and reset control attention when power on the resb pin must be set to ?low? level when power is firs t supplied. at that time, it is necessary to input a stable clock to the xin pin. you may input the voltage of vdd or less to each input terminal when the power supply is off. parameter symbol min typ max unit reset time(power on) tresw1 20 ms reset time(normal) (*1) tresw2 1 ms *1 : the oscillation must be stable during tresw2. when the xin clock has been stopped by the command etc. , the specification of tresw2 could be larger than the value shown above, because it takes time that the xin oscillator becomes stable. 3.3v power supply resb power on stage during normal operation (oscillation clock is valid) tresw1 tresw2
lc78616pe www.onsemi.com 12 host interface the four wires serial interface is available as the data transmission protocol between this lsi and host controller. it is able to know whether the in ternal sequencer could receive the command or not by the busyb pin. busyb command acceptance situation low all address command access disable high all address command access disabl e except a0h to a7h addresses busyb becomes low if the a5h address command is transmitted. all address command except a0h to a7h addresses will be ignored. by setting reg_ready command to high, internal register op en mode is available. in this mode, host controller can access to the all address command (internal sequencer can?t control the cddsp block). when the a5h address command is transmitted, reg_ready command and busyb pin is set to low, and internal register open mode become finish. ? command transfer timing 1 : (normal mode: busyb = "h" "l") ? command transfer timing 2 : (internal register open mode: busyb = "h") ce cl di busyb twh trd y off tcsu twl twsu twh d tch d trd y on trsu ce cl di busyb twh tcsu twl twsu twh d tch d tce trsu
lc78616pe www.onsemi.com 13 ? command receive timing 1 : (normal mode : busyb = "h" ) *1. high level must be supplied to the di pin during read access cycle. ? command receive timing 2 : (internal register open mode: busyb = "h") *1. high level must be supplied to the di pin during read access cycle. parameter symbol pin names min typ max unit setup time for ready trsu ce, busyb 60 ns setup time for ce tcsu ce, cl 400 hold time for ce tchd ce, cl 200 setup time for di twsu di, cl 100 hold time for di twhd di, cl 100 high level clock pulse width twh cl 200 low level clock pulse width twl cl 200 access time for read data trac cl, do 0 100 hold time for read data trhd cl, do 120 turn on time for do ton ce, do 150 turn off time for do toff ce, do 0 300 command transfer time tce ce 1 s turn off time for ready trdyoff ce, busyb 0 200 ns turn on time for ready(*1) trdyon ce, busyb 0.175 50000 s *1. never communicate in this period. ce cl di do busyb tcsu tce twh twl tch d toff trac trh d ton read setting cycle (write timing) read access cycle (*1) ce cl di do busyb tcsu tce twh twl tch d toff trac trh d ton read setting cycle (write timing) read access cycle (*1) ce cl di do busyb tcsu tce twh twl tch d toff trac trh d ton read setting cycle (write timing) read access cycle (*1)
lc78616pe www.onsemi.com 14 cd data output function two modes can be available for cd data output. (1) normal mode in this mode, output signals are lrck, bck and data . clv or jitter-free(vcec) playback is supported. when cdda playback, depending on the specification of audio dac, fs384 clock output is also available . (2) slave mode in this mode, output signal is data, and input signals are lrck, bck. the data output is synchronized to input clocks (lrck,bck). it is enable to output cd data synchronized to audio dac without connecting fs384clock. this mode is only available for cd normal playback, and lrck frequency must be 44.1 khz. 1. normal mode ? available format mode : iis, msb first right-justif ied, msb first left-justified slot length : 32 fs, 48 fs data length : 16-bit ? used pin lrcko : cont00, cont08 bcko : cont01, cont09 datao : cont02, cont10 ? note when cdda playback, fs384 can be optionally output from cont04 or cont05. the signal input from xin pin is output as fs384 signal. ? cd data output timing parameter symbol pin names min typ max unit bit clock frequency fa bcko bcko 10.5 mhz bit clock "h" level width tabkoh bcko 47.5 ns bit clock "l" level width tabkol bcko 47.5 ns setup time for lrck (based on bck negedge) tblp bcko, lrcko 0 15 ns hold time for lrck (based on bck negedge) tbla bcko, lrcko 0 15 ns setup time for data output tbds bcko, datao 30 ns hold time for data output tbdh bcko, datao 30 ns * in case of quadruple speed playback, and se tting the output format as 48fs slot length. lrcko bcko datao tabko tabko tblp tbds 1/fabck tbla tbdh
lc78616pe www.onsemi.com 15 2. slave mode in this mode, lrck (fs = 44.1 khz) and bck are input from external device, and output data is synchronized with input clocks. so, it is possible to play cdda without fs384 or src (sampling rate converter). ? available format mode : iis, msb first right-justif ied, msb first left-justified slot length : 32 fs, 48 fs, 64 fs data length : 16-bit ? used pin lrcki : cont00, cont08 bcki : cont01, cont09 datao : cont02, cont10 ? slave mode data timing parameter symbol pin names min typ max unit lrck frequency flrcki lrcki 44.1 48.5 khz lrck "h" level width tlrih lrcki 10.3 11.34 ? s lrck "l" leve l width tlril lrcki 10.3 11.34 ? s bit clock frequency fabcki bcki 2.1168 *1 3.10 mhz bit clock "h" level width tabkih bcki 160 236.2 *1 ns bit clock "l" level width tabkil bcki 160 236.2 *1 ns setup time for lrck input tbris lrcki, bcki 50 ns hold time for lrck input tblih lrcki, bcki 50 ns setup time for data output tdos datao, bcki 50 ns hold time for data output tdoh datao, bcki 50 ns *1: in case of setting the output format as 48 fs slot length. tdos tdoh lrcki (in) bcki (in) datao (out) tlrih tlril tabki tabkil 1/fabck 1/flrcki tblih tblis
lc78616pe www.onsemi.com 16 cd subcode data output function it is possible to output the subcode data (pw data) acc ording to the terminal setting when cd playback mode. the pw data are output at the rising edge of sbck signal when the sbck clock signal is input. the cd-text function and the cd subcode data output function are exclusive functions. it is impossible to use those two functions simultaneously. ? used pins sbsy (subcode block synchronous signal) : cont00 sfsy (subcode frame synchronous signal) : cont01 pw (subcode pw data) : cont02 sbck (subcode data read clock) : cont03 ? subcode data output timing ? subcode block synchronous signal output timing parameter symbol pin names min typ max unit subcode read cycle time tsbfc sfsy 136 *1 us subcode read enable time tsbe sfsy, sbck 400 ns sbck clock "h" level width tsbckh sbck 250 ns sbck clock "l" level width tsbckl sbck 250 ns pw data output delay time tsbrdl sbck, pw 0 100 ns sbsy output cycle time tsbbc sbsy 13.3 *2 ms sbsy "h" level width tsbbh sbsy 272 *2 us *1. when playback the cd at th e normal speed (clv playback). this value changes depending on the playback speed. *2. when playback the cd at th e normal speed (clv playback). the sbsy signal becomes high level during the first two subcoding symbols (s0 and s1) are asserted. sfsy (output) sbck (input) pw (output) tsbe p q r s t u v w "0" p tsbfc tsbckh tsbckl tsbrdl sbsy (output) tsbbc tsbbh
lc78616pe www.onsemi.com 17 cdtext data output function cdtext data are decoded and buffered to external sdram. there are two methods to output cdtext data from thesdram. (1) command communication output mode outputs the cdtext data using the command communication protocol between this ic and external host controller. (2) hand shake output mode usin g with hardware interface function a. inputs data request signal and tran sfer clock then outputs cdtext data the cdtext data(ctdato) will be output synchronizing with the ctcki clock when the ctcki clock is input after the cdtext data request signal is input(ctreqi = "h"). b. inputs data request signal then outp uts transfer clock and cdtext data the ctcko and ctdato synchronized with ctcko will be output after the cdtext data request signal is input (ctreqi = "h"). in both operation modes (1) and (2), the data transfer unit bit length is 2 bytes (16 bits). * the cdtext function and cd subcode data output function are exclusive each other, and then those functions can not be used simultaneously. ? cdtext data output timing 1 : ctck input mode both modes below are available. a. ctcki = "l" start mode the ctdato is output synchronized with the rising edge of the ctcki clock. the host controller should latch the ctdato da ta at the falling edge of the ctcki clock. b. ctcki = "h" start mode the ctdato is output synchronized with the falling edge of the ctcki clock. the host controller should latch the ctdato data at the rising edge of the ctcki clock. * the relationship between the signals in above timing chart and the pins is shown below. ctreqi : cont00, cont03, cont08 ctcki : cont01, cont04, cont09 ctdato : cont02, cont05, cont10 parameter symbol pin names min typ max unit ctcki clock frequency fsci ctcki 1.25 mhz ctcki clock input start time tctckin ctreqi, ctcki 1000 ns ctcki clock "h" level width tctckh ctcki 400 ns ctcki clock "l" level width tctckl ctcki 400 ns ctdato output dela y time tctdodl1 ctcki, ctdato 250 ns note : the above figure shows the case of mode a that the clock starts low level (ctcki = "l"). the timings are same when the clock starts high level (ctcki = "h"). ctreqi (input) ctcki (input) ctdato (output) tctdod tctckin tctckl 1/fsci tctck
lc78616pe www.onsemi.com 18 ? cdtext data output timing 2 : ctck output mod the ctcko will be output starting with the high level th en the ctdato will be output synchronized with the falling edge of the ctcko clock. the host controller should latch the ctdato data at the rising edge of the ctcko clock. * the relationship between the signals in above timing chart and the pins is shown below. ctreqi : cont00, cont03, cont08 ctcko : cont01, cont04, cont09 ctdato : cont02, cont05, cont10 parameter symbol pin names min typ max unit ctcko clock frequency fsco ctcko 1.05 4.2 mhz cdtext data output start time tctoat ctreqi, ctcko (1/fsco) 32 ns cdtext data output stop time tctoff ctreqi, ctcko (1/fsco) 32 ns ctcko clock "h" level width tctcoh ctcko 400 100 ns ctcko clock "l" level width tctcol ctcko 400 100 ns ctdato output delay time tctdodl2 ctdato, ctcko 0 50 ns tctdod ctreqi (input) ctcko (output) ctdato (output) tctcoh 1/fsco tctoat tctoff tctcol
lc78616pe www.onsemi.com 19 internal voltage regulator at ta = ? 40c to 85c, dv ss = av ss = xv ss = vv ss 1 = 0 v parameter symbol condition min typ max unit output voltage dvdd15 v dd = 3.0 to 3.6 v 1.35 1.50 1.65 v load current iope v dd = 3.3 v 50 ma ? example circuit for regulator a/d, d/a converter characteristics for servo at ta = ? 40c to 85c, v dd = 3.3 v, dv ss = av ss = xv ss = vv ss 1 = 0 v parameter symbol min typ max unit resolution res 8 bit maximum input/output range vaio1 4/5 ? v dd v minimum input/output range vaio2 1/5 ? v dd v oscillator ? example circuit for oscillator xin/xout : 16.9344 mhz ? for system clock of internal micro co ntroller, cd control and audio control ? recommended oscillators murata manufacturing co., ltd. smd : cstce16m9v53-r0 : cstcw16m9x51008-r0 lead : cstls16m9x53-b0 ? because the characteristics of oscillator could be changed according to the circuit board, ask evaluation with the individual original circuit board to the oscillator maker. ? concerning about internal circuit for xin/xout, refer to the "ana log pin internal equivale nt circuits" section. the xin pin can also be supplied from an external clock instead of connecting the oscillator. in this case, xout pin must be left open. xvdd xin xout xvss lc78616 c1 c1 rd1 dvdd dvss dvdd15 lc78616 100 ? f * same circuit need to be mounted both for two regulator pins. (no.28 and no.61) * c1 is the capacitor to avoid oscillation. this capacitor value must be low esr and greater than 30 ? f in the range of the operating temperature. because there is a possibility of the oscillation when the capacity value changes by the temperature change etc. (the recommended value is 100 ? f. ) c1
lc78616pe www.onsemi.com 20 sdram interface (1) required specification for external sdram memory size : 16m-bit or 64m-bit data width : 16-bit cas latency : 2 burst length : full (2) interface pins to external sdram pin name function at 16m-bit-sdram function at 64mbit-sdram signal name in timing chart (page21,22) sddat15 to sddat00 data input/output (16-bit) data input/output (16-bit) ddat[15:0] ddat[15:0] sdadrs10 to sdadrs00 address output (11-bit) address output (11-bit) dadd[10:0] dadd[10:0] sdadrs11 not used *1 address(a11) output ? dadd[11] sdadrs12 not used *2 address(a12) or bank0 output ? dadd[12] sdba bank output bank or bank1 output dadd[11] dadd[13] sddqm dqmh/dqml (udqm/ldqm) output *3 dqmh/dqml (udqm/ldqm) output *3 sddqm sddqm sdcsb csb output csb output sdcsb sdcsb sdrasb rasb output rasb output sdrasb sdrasb sdcasb casb output casb output sdcasb sdcasb sdweb web output web output sdweb sdweb sdcke clock enable output clock enable output sdcke sdcke sdclk clock output clock output sdclk sdclk *1. sdadrs11 in 16m-bit sdram using mode can be used as cont06 pin. *2. sdadrs12 in 16m-bit sdram using mode can be used as cont07 pin. *3. the sdram access data width of this ic is sixteen bits. therefore, conn ect the sddqm of th is ic to both the dqmh(udqm) and dqml(ldqm) pins of sdram. *4. the all pins used for sdram interface are input pin mode a nd internal pull down resistor on mode in initial condition after reset of this ic. all the resistors will be of f when the sdram use mode is set to be on. *5. some signals used in timing chart (p21,22) use different pins according to the using sdram. the signal name the actual pin is shown at the most right column in above table. upper step : signal name in 16mbit-sdram using mode lower step : signal name in 64mbit-sdram using mode
lc78616pe www.onsemi.com 21 (3) sdram access timing ? sdram read timing ? sdram write timing all-pre column ts7 sdcsb sdclk sdcke sdrasb sdcasb sdweb dadd[13:0] sddqm ddat[15:0] ts5 row read-data 1/fs1 ts4 ts8 ts11 cas-latency 2 ts2 ts3 ts5 ts6 ts7 ts5 ts6 ts7 ts9 - ts10 column row ts6 write-data all-pr e column ts7 sdcsb sdclk sdcke sdrasb sdcasb sdweb dadd[13:0] sddqm ddat[15:0] ts5 ts6 row 1/fs1 ts8 data latch timing (sdram) ts2 ts3 ts5 ts6 ts7 ts5 ts6 ts7 ts9 ts13 ts12 row column a ll-pre write-data
lc78616pe www.onsemi.com 22 ? sdram refresh timing (auto refresh) symbol parameter min typ max unit fs1 sdram clock(sdclk) frequency 16.9344 mhz ts2 row(sdrasb) cycle time (1/fs1)5 ? ? ns ts3 row(sdrasb) active time (1/fs1)3 ? ? ns ts4 rasb-casb delay time(sdrasb-sdcasb) (1/fs1)2 ? ? ns ts5 command "l" level width (sdcsb, sdcke, sdrasb, sdcasb, sdweb) 40 ? ? ns ts6 command setup time (sdcsb, sdcke, sdrasb, sdcasb, sdweb, sddqmu, sddqml) 10 ? ? ns ts7 command hold time (sdcsb, sdcke, sdrasb, sdcasb, sdweb, sddqmu, sddqml) 10 ? ? ns ts8 address(dadd) setup time 10 ? ? ns ts9 address(dadd) hold time 10 ? ? ns ts10 sdram read data setup time (data read from sdram) 20 ? ? ns ts11 sdram read data hold time (data read from sdram) 0 ? ? ns ts12 sdram write data hold time before rising edge of sdclk (data write to sdram) 10 ? ? ns ts13 sdram write data hold time after rising edge of sdclk (data write to sdram) 10 ? ? ns ts14 row(sdrasb) pre-charge time (1/fs1)3 ? ? ns ts15 row(sdrasb) active time after refresh (1/fs1)5 ? ? ns ? setup time and hold time specifications in above table are measured from the rising edge of sdclk signal. ? all the specifications in above table are appl ied to read mode, write mode and refresh mode. ts7 sdcsb sdclk sdcke sdrasb sdcasb sdweb dadd[13:0] sddqm ddat[15:0] ts5 ts6 1/fs1 ts15 ts14 ts5 ts6 ts7
lc78616pe www.onsemi.com 23 analog pin internal equivalent circuits pin name (pin no.) equivalent circuit efmin (81) avdd avss rfout (82) avdd avss avdd avss lpf (83) avdd avss avdd avss phlpf (84) avdd avss ain (85) cin (86) bin (87) din (88) avdd avss slciset (89) avdd avss rfmon (90) avdd avss avdd avss
lc78616pe www.onsemi.com 24 pin name (pin no.) equivalent circuit vref (91) avdd avss avdd avss jittc (92) avdd avss ein (93) fin (94) te (96) avdd avss avdd avss tein (97) avdd avss ldd (98) avdd avss avdd avss avdd lds (99) avdd avss
lc78616pe www.onsemi.com 25 pin name (pin no.) equivalent circuit fdo (2) tdo (3) sldo (4) spdo (5) avdd avss avdd avss pdout1 (7) vvdd1 vvss1 vvdd1 vvss1 pdout0 (8) vvdd1 vvss1 vvdd1 vvss1 pckist (9) vvdd1 vvss1 vvss1 xout(72) xin(73) xvdd xvss xvss xvdd xin xout slco (80) avdd avss avdd avss
lc78616pe www.onsemi.com 26 sample application circuit * this sample circuit is only for cd servo block and each pll block. the value of each component needs to be adjusted under the target conditions. the circuit for cd servo shown above could be changed depending on the cd mechanism used. 16.9344mhz a ( ) b ( ) c ( ) d ( ) vref (reference voltage) e ( ) f ( ) ld md efmin rfout lpf phlpf ain cin bin din slciset rfmon vref jittc ein fin nc te tein ldd lds avss slco dvss cont10 cont09 cont08 dvdd xvdd xin xout xvss 80 79 78 77 76 75 74 73 72 71 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 vref fdo tdo sldo spdo to pickup vdd gnd to d r i v e r lc78616 6dxx gnd avdd fdo tdo sldo spdo vvss1 pdout1 pdout0 pckist vvdd1 mode ce cl di do resb test busyb to ? -com
lc78616pe www.onsemi.com 27 on semiconductor and the on semiconductor logo are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries in the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and othe r intellectual property. a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does on semiconductor assume any liability arising out of the app lication or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, regulations and safety require ments or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the rights of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life sup port systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended fo r implantation in the human body. should buyer purchase or use on semiconductor products for any such unintended or unauthorized application, buyer sh all indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, d amages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resal e in any manner. ordering information device package shipping (qty / packing) lc78616pe-6d02-h pqfp100 14x20 / qip100e (pb-free / halogen free) 250 / tray foam

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